Personal computer systems in general and IBM personal computers in particular have attained widespread use for providing computer power to many segments of today's modern society. Personal computer systems can usually be defined as a desk top, floor standing, or portable microcomputer that consists of a system unit having a single system processor and associated volatile and non-volatile memory, a display monitor, a keyboard, one or more diskette drives, a fixed disk storage, and an optional printer. One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to electrically connect these components together. These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM/2 Models 25, 30, 50, 60, 70 and 80.
These systems can be classified into two general families. The first family, usually referred to as Family I Models, uses an expansion bus architecture exemplified by the IBM PERSONAL COMPUTER AT and other "IBM compatible" machines. The second family, referred to as Family II Models, uses IBM's MICRO CHANNEL expansion bus architecture exemplified by IBM's PERSONAL SYSTEM/2 Models 50 through 80. The Family I models typically have used the popular Intel Corporation 8088 or 8086 microprocessor as the system processor. These processors have the ability to address one megabyte of memory. The Family II models typically use the high speed Intel Corporation 80286, 80386, and 80486 microprocessors which can operate in a real mode to emulate the slower speed Intel Corporation 8086 microprocessor or a protected mode which extends the addressing range from 1 megabyte to 4 Gigabytes for some models. In essence, the real mode feature of the 80286, 80386, and 80486 processors provides hardware compatibility with software written for the 8086 and 8088 microprocessors.
In both Families, the expansion bus has a straightforward purpose--enabling the use of option or expansion cards or boards to add features or options and expand the usefulness of the system. As expansion bus architectures have developed, provision has been made for a number of functions to be served by the multiple channels provided. These functions have included data read and write commands issued by the microprocessor, direct memory access commands for moving data, and interrupt requests by which various devices may capture the attention of the microprocessor and divert it to another task. In the handling of interrupt requests, the microprocessor becomes a server and other devices connected with the bus become clients. In order to attain high system throughput, it is desirable for the system to detect, service and reset interrupt signals as promptly as feasible. Thus there are three areas of interrupt signal handling which can be addressed in optimizing system performance, namely the detection, servicing and resetting of interrupt signals impinging on the microprocessor. Prior to the present invention, interrupt handling has been essentially seriatim, opening the probability that throughput may be severely impaired by the occurrence of a large number of logical interrupts which require resetting by successive addressing of a plurality of devices which deliver such logical interrupts through a single interrupt pathway or a limited small number of such pathways. This impairment becomes particularly serious with an architecture in which control over data buses is shared among a plurality of devices, each of which may take control of the data bus. Such devices are known as "bus masters".